1. Field of the Invention
This invention pertains to a large swing input/output analog buffer, and more particularly to a large swing input/output analog buffer that has a push-pull output stage which provides the buffer with improved performance characteristics and low power consumption. The large swing input/output analog buffer of this invention is designed to be used in many applications including scanners and other imaging devices.
2. Description of the Related Art
Analog buffer circuits are widely used in analog circuit design. Such buffers typically have high input impedance and low output impedance to provide high speed and large driving ability. The buffers are used to provide an output signal which tracks its input signal.
FIG. 1 shows one such conventional analog buffer, identified generally by the reference numeral 11. Analog buffer 11 has both an n-input stage and a n-input stage, as well as a bias circuit and an output stage. Two voltage sources, VDD and VSS, may be used to power the circuit. Alternatively, only VDD may be used with VSS grounded.
The n-input stage includes a pair of NMOS input transistors N1 and N2 which receive input voltage signals INN and INP respectively. The n-input stage further includes two PMOS load transistors, P3 and P4, connected in current mirror configuration. Current source transistor N5 is connected in current mirror configuration with transistor N6 in then bias circuit. A reference current (IREF) is supplied to the drain of N6 to induce a current in N5 as a result of the current mirror connection between these two transistors.
In addition to N6, the bias circuit further comprises transistor N7, which also forms a current mirror with N6, and a third transistor P8 whose gate and drain are coupled to the drain of N7. The gate and drain of P8 are also connected to the gate of current source transistor P9 in the p-input stage to form a current mirror. As a result of this connection, then current in P8 induces a current in P9 to provide a source current for the p-input stage.
The p-input stage further includes a pair of PMOS input transistors P10 and P11 which receive input voltage signals INN and INP respectively. Two NMOS load transistors N12 and N13, interconnected in current mirror configuration, are also provided.
The n- and p-input stages generate voltage signals OUTPPX and OUTNNX respectively. OUTPPX is applied to the gate of transistor P14 and OUTNNX is applied to the gate of N16. These two transistors collectively comprise the output stage of analog buffer 11. The nodes where OUTPPX and OUTNNX are generated are also coupled through capacitors C1 and C2 to the common drain connection between the two output transistors. This common drain connection also forms the output node from which output voltage signal OUTP is taken.
In accordance with analog buffer operation, the output node where voltage signal OUTP is generated is connected to the node where input voltage signal INN is applied to provide a bi-directional driving current which gives the buffer 11 a relatively fast settling time for charging and discharging load capacitances (up to 5 pF). In this case, INTP is the input signal. However, because the nodes where voltages OUTPPX and OUTNNX are generated are floating, those voltages can fluctuate over a very large range. This can cause the NMOS transistor, N16, which is gated by OUTNNX, to fully turn on when INP is relatively high (i.e., near VDD) and PMOS transistor P14, which is gated by OUTPPX, to fully turn on when INP is relatively low (i.e., near VSS). This, in turn, will limit the output range so that OUTP does not closely track INP at the high and low ends of the voltage range and will also lower the driving ability of the buffer 11. This will also cause the buffer 11 to draw a large dc current from the power supply even when the buffer 11 is in an idle state (i.e., no input signal is applied).